Phase-Locked Loop Synthesizer Simulation

Phase Locked Loop frequency synthesis is a key component of all wireless systems. This is a complete toolkit for PLL synthesizer design, with MathCAD, SIMetrix files included on CD, allowing readers to perform sophisticated calculation and simulation exercises.

Describes how to calculate PLL performance by using standard mathematical or circuit analysis programs

• Open loop, closed loop, and phase error response calculations
• Noise definition and analysis
• Direct Digital Synthesizer
• CD containing all Mathcad and SIMetrix files to perform all analyses described in the book. Readers can play with them, modify values and/or configurations in order to adapt to different PLL.
• Mathcad and SIMetrix demo versions